Twin-Cell Semiconductor Memory Devices

ABSTRACT

Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 120 as a continuationapplication of U.S. patent application Ser. No. 11/094,948, filed Mar.31, 2005, which in turn claims priority under 35 U.S.C. § 119 fromKorean Patent Application No. 2004-0055770, filed Jul. 16, 2004. Thedisclosures of each of the above applications are hereby incorporated byreference herein as if set forth in their entireties

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and, moreparticularly, to semiconductor memory devices.

BACKGROUND OF THE INVENTION

Magnetic random access memory (MRAM) devices are non-volatile memorydevices that use a magnetoresistance effect to store information. InMRAM devices, the resistance of an electrical conductor is changed inresponse to a circumferential magnetic field to store information. TheMRAM devices may include a plurality of MRAM cells, each of which mayinclude a magnetic tunnel junction (MTJs), on a single transistor.

The MTJ may include a plurality of thin layers. In particular, electronsmay tunnel through a very thin insulating layer that is sandwichedbetween, for example, two ferromagnetic electrodes in response to theapplication of an external electrical signal. Conventionally, the topelectrode is called a free layer and the bottom electrode is called apinned layer.

When the direction of the magnetic fields within the free layer and thepinned layer are arranged to be parallel to each other, the tunnelingcurrent that flows through the MTJ may tend towards its maximum value,and the tunneling resistance may tend towards its minimum value in thissituation. On the other hand, when the direction of the magnetic fieldswithin the free layer and the pinned layer are arranged to beperpendicular to each other, the tunneling current that flows throughthe MTJ may tend towards its minimum value, and the tunneling resistancewill typically tend towards its maximum value in this situation.

Digital data (i.e., “0” and “1” data) may be stored in the MTJ bydesignating the low resistance state where the magnetization directionsof the two electrodes are parallel to each other as one of the binarystates and the high resistance state where the magnetization directionsof the two electrodes are perpendicular to each other as the other ofthe binary states. In such devices, there are two cell types that arewidely used to read the “0” and “1” states. These cell types arecommonly referred to as a reference cell type and a twin cell type.

One method for reading digital data out of an MRAM cell is disclosed inU.S. Pat. No. 6,496,436 B2 to Niji, entitled “Reference VoltageGenerator for MRAM and Method.” Pursuant to this method, the MRAM deviceincludes MRAM cells that are connected to at least one bit line, and areference column that is disposed adjacent to the bit line that includesa reference voltage generator. The reference voltage generator includesa plurality of MTJs. Each of the MTJs connected to the reference voltagegenerator is set to have either a maximum resistance or a minimumresistance. These MTJs are then interconnected to provide anintermediate value of reference resistance between the maximum andminimum values. Both the bit line and the reference column are connectedto a sense simplifier. An electrical signal output from one of the MRAMcells connected to the bit line may be compared with an electricalsignal output from the reference column that is commonly connected tothe sense amplifier. In this fashion, a low resistance state may bediscriminated from a high resistance state to determine whether a “0” or“1” is stored in the selected MRAM cell.

A problem, however, may arise when using the above-described referencecell method for reading data from an MRAM cell. The current that is usedto read data from the cell flows through a tunneling layer of the MTJ.An insulating layer, such as an aluminum layer, is widely used as thetunneling layer. Thus, the resistance value of the MTJ may be the sum ofthe resistance value of the tunneling layer and the resistance valuethat results from the arrangement of the magnetization directions withinthe free layer and the pinned layer. The resistance value of thetunneling layer, however, may vary with the thickness of the tunnelinglayer. The thickness of the tunneling layer typically is not constantbecause of manufacturing variation. Consequently, the resistance of theMTJ will often vary between MTJ cells due to variations in the thicknessof the tunneling layer.

The above-described variation in the resistance of MTJ cells may make itdifficult to use the reference cell approach for reading data from MRAMdevices. The reason for this is that, for proper operation of thedevice, the change in the magnetoresistance of the MTJ that occurs whenthe direction of the magnetic fields in the MTJ are switched fromparallel to perpendicular to each other is not sufficiently larger thanthe change in the resistance value of the tunneling layer that can beexpected due to expected manufacturing variation using conventional massproduction manufacturing techniques.

Because of the above-mentioned problem with the reference cell method ofreading data from an MRAM cell, twin cell methods of reading data fromMRAM devices have been suggested. In twin cell MRAM devices, one bit ofdata is written (i.e., stored) in two MTJs by writing the data bit to afirst MTJ and writing a complementary data bit to the second MTJ. Bothdata bits may then be read by comparing the resistance of each MTJ cellto the reference cell. Consequently, in twin cell MRAM devices theamount of magnetoresistance change is doubled and hence is lesssensitive to the “noise” that may be introduced by manufacturingvariations in the thickness of the tunneling layers.

FIG. 1 is a circuit diagram of a prior art twin cell MRAM device. FIG. 2is an enlarged view of a portion of the circuit diagram of FIG. 1. Asshown in FIG. 1, the twin cell type MRAM device may include a pluralityof parallel bit lines B01, B11, B02, B12 which are arranged to formcolumns, and a plurality of parallel word lines Wi, Wj which arearranged to form rows. In addition, a plurality of digit lines Di, Djmay be provided which cross the bit lines B01, B11, B02, B12. MTJs areprovided at the intersections of the bit lines B01, B11, B02, B12 andthe digit lines Di and Dj, respectively. Each MTJ is connected to anaccess transistor TA. As shown in FIG. 1, one end of each MTJ isconnected to one of the access transistors TA and the other end of theMTJ is connected to one of the bit lines B01, B11, B02, B12. The gateelectrode of each of the access transistors TA is connected to one ofthe word lines Wi, Wj. Adjacent bit lines B01, B11 are connected tosense amplifier SA1 to form a first bit line pair and bit lines B02, B12are connected to sense amplifier SA2 to form a second bit line pair.

As noted above, each MTJ is connected to one of the bit lines B01, B11,B02, B12. As shown by the dotted line box labeled “A” in FIG. 1, theMTJs are arranged as pairs of MTJs that are used to store complementaryinformation. For example, when the pair of MTJs “A” is programmed, adigit line program current is applied to the selected digit line Di, anda bit line program current is applied to the pair of bit lines B01 andB11. The bit line program current is applied in a forward direction toone of the pair of MTJs and is applied in a reverse direction to theother of the pair of MTJs. As a result, the data stored in the first ofthe MTJs is the opposite of the data stored in the second of the MTJs inthe pair of MTJs “A”.

To read the data stored in the MTJ pair labeled “A”, the electricalpotentials of the pair of bit lines B01 and B11 are compared by thefirst sense amplifier SA1 and read as one bit of data.

As shown in FIG. 7, a first magnetic tunnel junction Mi is arranged atthe intersection of the first bit line B01 and the digit line Di, and asecond magnetic tunnel junction Mj is arranged at the intersection ofthe second bit line B11 and the digit line Di. When the first magnetictunnel junction Mi is programmed, a digit line program current isapplied to the digit line Di, and a forward bit line program current I0is applied to the first bit line B01. Simultaneously, a reverse bit lineprogram current I1 is applied to the second bit line B11. The forwardbit line program current I0 induces a forward magnetic field FT to thefirst bit line BUT, and the reverse bit line program current I1 inducesa reverse magnetic field FS′ to the second bit line B11. Consequently,the first magnetic tunnel junction Mi and the second magnetic tunneljunction Mj are magnetized in opposite directions. For example, if themagnetization directions within the pinned layer and the free layer ofthe first magnetic tunnel junction Mi are arranged in parallel, themagnetization directions within the pinned layer and the free layer ofthe second magnetic tunnel junction Mj will be arranged to beperpendicular to each other. If instead, the magnetization directionswithin the pinned layer and the free layer of the first magnetic tunneljunction Mi are arranged to be perpendicular to each other, themagnetization directions within the pinned layer and the free layer ofthe second magnetic tunnel junction Mj are arranged parallel to eachother.

SUMMARY OF THE INVENTION

Pursuant to embodiments of the present invention, semiconductor memorydevices are provided that include a plurality of main bit lines and aplurality of reference bit lines. In these devices, each of thereference bit lines correspond to respective ones of the main bit linesto form a plurality of bit line pairs. A plurality of sense amplifiersare provided that are electrically connected to respective ones of theplurality of bit line pairs. In these devices, at least one of theplurality of main bit lines or the plurality of reference bit lines isinterposed between the main bit line and the corresponding reference bitline of each bit line pair. At least some of the main bit lines maycross respective ones of the reference bit lines in a sense amplifierregion of the semiconductor memory device.

In certain embodiments of the present invention, the semiconductormemory device may further include a plurality of word lines that crossthe main bit lines and the reference bit lines. A plurality of memorycells are arranged at respective intersections of the reference bitlines and the word lines and at the intersections of the main bit linesand the word lines. Each memory cell may be electrically connected toone of the word lines and to one of the main bit lines or the referencebit lines. In these devices, the plurality of memory cells may be, forexample, magnetic random access memory (MRAM) cells, ferroelectricrandom access memory (FeRAM) cells, phase change random access memory(PRAM) cells, or dynamic random access memory (DRAM) cells.

In specific embodiments, a total of two bit lines—which may be two mainbit lines, two reference bit lines, or one of each—may be interposedbetween the main bit line and the corresponding reference bit line ofeach bit line pair. In other embodiments, a total of three bit lines(any combination) may be interposed between the main bit line and thecorresponding reference bit line of each bit line pair. Larger number ofbit lines may also be interposed, and the same number of bit lines doesnot need to be interposed between the bit lines that form each bit linepair.

In embodiments of the present invention that include MRAM memory cells,each of the MRAM cells may include a magnetic tunnel junction (MTJ). TheMTJ may include a bottom electrode, a pinning layer pattern, a pinnedlayer pattern, a tunnel layer pattern, and a free layer pattern whichare sequentially stacked.

In certain embodiments of the present invention, the top surfaces andsidewalls of the bit walls may be surrounded by a cladding pattern. Thesemiconductor memory device may also include a plurality of digit linesthat cross the main bit lines and the reference bit lines. These digitlines may have bottom surfaces and sidewalls surrounded by a claddingpattern.

Pursuant to further embodiments of the present invention, semiconductormemory devices are provided which include a plurality of MRAM main cellsand a plurality of MRAM reference cells that are grouped in pairs toform a plurality of MRAM cell pairs, each of which are configured totogether store a single bit of data. At least one of the plurality ofMRAM main cells and/or at least one of the plurality of MRAM referencecells is interposed between the one of the MRAM main cells and the oneof the MRAM reference cells that form each MRAM cell pair. In certainembodiments of the present invention, the semiconductor memory devicemay further include a plurality of parallel bit lines and a plurality ofparallel word lines. The plurality of M MRAM main cells and a pluralityof MRAM reference cells may be arranged such that each MRAM main celland each MRAM reference cell is electrically connected to one of theplurality of bit lines and to one of the plurality of word lines. Thetwo MRAM cells that form each MRAM cell pair may be electricallyconnected to the same word line. The device may further include aplurality of sense amplifiers, and the MRAM cells may be electricallyconnected to respective ones of the plurality of sense amplifiers suchthat the two MRAM cells that form each MRAM cell pair are electricallyconnected to the same sense amplifier.

In still further embodiments of the present invention, semiconductormemory devices are provided which include a plurality of main bit linesand a plurality of reference bit lines. Each of the reference bit linesis associated with a corresponding one of the plurality of main bitlines such that the main bit lines and the reference bit lines aregrouped form a plurality of bit line pairs. A plurality of word linesare also provided that cross (he main bit lines and the reference bitlines. A plurality of memory cells are electrically connected torespective of the plurality of word lines and to respective of the mainbit lines or the reference bit lines. Additionally, the bit lines arearranged such that at least one of the bit lines of each bit line paircrosses over one of the bit lines of another of the bit line pairs.

In specific embodiments, each of the memory cells may be locatedadjacent the intersection of one of the word lines and either one of themain bit lines or one of the reference bit lines. The device may alsoinclude a plurality of sense amplifiers, and the main bit line and thereference bit line of each bit line pair may be electrically connectedto a corresponding one of these sense amplifiers. Each memory cell maybe an MRAM cell that includes a magnetic tunnel junction and an accesstransistor that are electrically connected to each other. Moreover, thememory cells may be categorized as main memory cells and referencememory cells, and each main memory cell may correspond to a respectiveone of the reference memory cells to form a plurality of memory cellpairs, and at least one other memory cell may be interposed between thetwo memory cells that form each memory cell pair.

In still further embodiments of the present invention, semiconductormemory devices are provided that include a memory cell array region andfirst, second, third and fourth bit lines, each of which cross over thememory cell array region in a first direction. First and second wordlines are provided that cross over the memory cell array region in asecond direction that is approximately perpendicular to the firstdirection. In these devices, the first bit line is adjacent the secondbit line in the memory cell array region and is adjacent to the thirdbit line in a second region of the device whereas the fourth bit line isadjacent the third bit line in the memory cell array region and isadjacent to the second bit line in the second region of the device.

The memory cell array region may include a first memory cell that islocated adjacent the intersection of the first bit line and the firstword line, a second memory cell that is located adjacent theintersection of the first bit line and the second word line, a thirdmemory cell that is located adjacent the intersection of the second bitline and the first word line, a fourth memory cell that is locatedadjacent the intersection of the second bit line and the second wordline, a fifth memory cell that is located adjacent the intersection ofthe third bit line and the first word line, a sixth memory cell that islocated adjacent the intersection of the third bit line and the secondword line, a seventh memory cell that is located adjacent theintersection of the fourth bit line and the first word line, and aneighth memory cell that is located adjacent the intersection of thefourth bit line and the second word line. The device may further includea sense amplifier region that includes a first sense amplifier that iselectrically connected to the first, second, fifth and sixth memorycells and second sense amplifier that is electrically connected to thethird, fourth, seventh and eighth memory cells. The second region may bethe region that includes the first and second sense amplifiers.

In specific embodiments, the second and third bit lines may cross in ornear the second region. The first and second bit lines may comprise afirst main bit line and a second main bit line, respectively, and thethird and fourth bit lines may comprise a first reference bit line and asecond reference bit line, respectively. The first memory cell and thefifth memory cell may be configured to together store a first data bit,the second memory cell and the sixth memory cell may be configured totogether store a second data bit, the third memory cell and the seventhmemory cell may be configured to together store a third data bit, andthe fourth memory cell and the eighth memory cell may be configured totogether store a fourth data bit.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate certain embodiment(s) of theinvention. In the drawings:

FIG. 1 is a circuit diagram of a conventional prior art twin cell typeMRAM device.

FIG. 2 is a more detailed circuit diagram of a portion of the circuit ofFIG. 1.

FIG. 3 is a circuit diagram illustrating a semiconductor memory devicein accordance with certain embodiments of the present invention.

FIG. 4 is a cross-sectional view illustrating a MRAM cell in accordancewith certain embodiments of the present invention.

FIG. 5 is a distribution chart of bit failures of a semiconductor memorydevice fabricated in accordance with embodiments of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when all element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(i.e., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer or region to another element, layer or region asillustrated in the figures. It will be understood that these terms areintended to encompass different orientations of the device in additionto the orientation depicted in the figures.

It also will be understood that: as used herein, the terms “row” and“column” indicate two non-parallel directions that may be orthogonal toone another. However, the terms row and column do not indicate aparticular horizontal or vertical orientation.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention.The thickness of layers and regions in the drawings may be exaggeratedfor clarity. Additionally, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a binary change from implanted to non-implanted region.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as welt, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 3 is a circuit diagram illustrating a semiconductor memory devicein accordance with certain embodiments of the present invention.

As shown in FIG. 3, the memory device includes a main bit line region Mand a reference bit line region R. A first main bit line MB1 and asecond main bit line MB2 are disposed parallel to each other alongcolumns in the main bit line region M. A first reference bit line TB1and a second reference bit line TB2 are disposed parallel to each otherand parallel to the main bit lines MB1 and MB2 in the reference bit lineregion R. The first main bit line MB1 and the first reference bit lineTB1 form a first bit line pair, and the second main bit line MB2 and thesecond reference bit line TB2 form a second bit line pair. It will beappreciated that typically far more than two pairs of bit lines (andmore than two word lines) will be provided in the MRAM device.

A plurality of sense amplifiers are electrically connected to the mainbit lines and the reference bit lines. For example, as shown in FIG. 3,the first main bit line MB1 and the first reference bit line TB1 areconnected to a first sense amplifier S1, and the second main bit lineMB2 and the second reference bit line TB2 are connected to a secondsense amplifier S2.

A plurality of word lines may be provided that cross the main andreference bit lines. For example, in the embodiment of FIG. 3, a firstword line W1 and a second word line W2 cross the main bit lines MB1 andMB2 and the reference bit lines TB1 and TB2. First to fourth main cellsMC1, MC2, MC3, MC4 are arranged at intersections of the main bit linesMB1 and MB2 and the word lines W1 and W2. Additionally, first to fourthreference cells TC1, TC2, TC3, TC4 are arranged at intersections of thereference bit lines TB1 and TB2 and the word lines W1 and W2.

The first main bit line MB1 and the first reference bit line TB1 operateas one bit line pair, and the second main bit line MB2 and the secondreference bit line TB2 operate as another bit line pair. Likewise, thefirst main cell MC1 and the first reference cell TC1 operate as onememory cell pair that store respective data which are always opposite toeach other, and the second main cell MC2 and the second reference cellTC2 operate as another memory cell pair that store respective data whichare always opposite to each other. To read the stored data from thefirst of these memory cell pairs, the electrical potential of the firstmain bit line MB1 connected to the first main cell MC1 and theelectrical potential of the first reference bit line TB1 connected tothe first reference cell TC1 are compared by the first sense amplifierS1 such that the two potentials are read as one bit of data.

When the first main bit line MB1 and the first reference bit line TB1are operated as a pair, an electrical signal is not applied to thesecond main bit line MB2 disposed between the first main bit line MB1and the first reference bit line TB1. Thus, interference between thefirst main bit fine MB1 and the first reference bit line TB1 may bereduced. Accordingly, at least one other bit line may be disposedbetween the first main bit line MB1 and the first reference bit line TB1as shown in FIG. 3. The at least one other bit line may be the secondmain bit line MB2 as shown in FIG. 3, or may be the second reference bitline TB2. Alternatively, the at least one other bit line may be composedof a plurality of other bit lines.

The main cells MC1, MC2, MC3, MC4 and the reference cells TC1, TC2, TC3,TC4 may comprise magnetic random access memory (MRAM) cells,ferroelectric random access memory (FeRAM) cells, phase change randomaccess memory (PRAM) cells, or dynamic random access memory (DRAM)cells.

In the description of some embodiments of the present invention below,the main cells MC1, MC2, MC3, MC4 and the reference cells TC1, TC2, TC3,TC4 comprise MRAM cells which each include a MTJ and an accesstransistor TA connected to a bottom electrode of the MTJ.

FIG. 4 is a cross-sectional view illustrating a MRAM cell in accordancewith certain embodiments of the present invention. As shown in FIG. 4,the MRAM cell includes an access transistor TA on a predetermined regionof a semiconductor substrate 51. The access transistor TA includes asource region 52S, a drain region 52D, a channel region between thesource and drain regions and a gate electrode 55 disposed above thechannel region that may act as a word line. A digit line 62 is disposedabove the access transistor TA. The digit line 62 is arranged parallelto the word line.

The bottom surface and sidewalls of the digit line 62 may be surroundedby a cladding pattern. The digit line 62 may be a conductive layer suchas a copper layer or an aluminum layer. The cladding pattern may beformed of a ferromagnetic layer such as NiFe. The cladding pattern mayfocus the magnetic flux generated by the current flowing through thedigit line 62.

A MTJ 70 is disposed above the digit line 62 and opposite to the accesstransistor TA. In the embodiment of FIG. 4, the MTJ 70 is a stackedstructure which includes a bottom electrode 63, a pinning layer pattern65, a pinned layer pattern 66, a tunneling layer pattern 67, a freelayer pattern 68, and a top electrode 69 which are sequentially stacked.A layer of insulating material is interposed between the digit line 62and the bottom electrode 63 which may act to insulate the MTJ 70 fromthe digit line 62. The bottom electrode 63 may be electrically connectedto the drain region 52D through a contact plug 61 or other electricalpath, or may be in direct contact with the drain region 52D.

The top electrode 69 is electrically connected to the bit line 72 thatcrosses the digit line 62. The top surface and sidewalls of the bit line72 may be surrounded by a cladding pattern. The bit line 72 may be aconductive layer such as a copper layer or an aluminum layer. Thecladding pattern may comprise, for example, a ferromagnetic layer suchas NiFe. The cladding pattern may act to focus a magnetic flux generatedby the current flowing through the bit line 72.

The pinning layer pattern 65 may comprise an anti-ferromagnetic layer,and the pinned layer pattern 66 and the free layer pattern 68 maycomprise ferromagnetic layers. The pinning layer pattern 65 may act tofix the magnetization direction of the pinned layer pattern 66. Inparticular, the pinned layer pattern 66 may halve a large switchingfield, and the magnetization direction of the pinned layer pattern 66may be fixed in a constant direction when an applied magnetic field issmaller than the switching field. The pinned layer pattern 66 may have astructure composed of one ferromagnetic layer, or a syntheticanti-ferromagnetic (SAF) structure including three layers. The SAFstructure may include a bottom pinned layer and a top pinned layer whichare separated by an exchange spacer layer. Each of the bottom pinnedlayer and the top pinned layer may be a ferromagnetic layer. Theexchange spacer layer may be a ruthenium (Ru) layer. The SAM structurehas a characteristic that the magnetization directions of the bottom andtop pinned layers are arranged to be perpendicular to each other due tothe effect of the exchange spacer layer. That is, when an initialmagnetization direction is applied to the bottom pinned layer, themagnetization direction of the top pinned layer is arranged in aperpendicular state.

When the MRAM cell operates in program mode, the program current flowsthrough the bit line 72 and the digit line 62 to magnetize the freelayer pattern 68. The magnetization direction forced within the freelayer pattern 68 during the operation in program mode is determined bythe direction of the program current flowing through the bit line 72,and will be parallel or perpendicular to the magnetization directionmaintained within the pinned layer pattern 66. When magnetized spinswithin the free layer pattern 68 are arranged parallel to spins fixedwithin the pinned layer pattern 66, the tunneling layer pattern 67 willshow a decreased magnetoresistance value. When, on the other hand, themagnetized spins within the free layer pattern 68 are arrangedperpendicular to the spins fixed within the pinned layer pattern 66, thetunneling layer pattern 67 will show an increased magnetoresistancevalue.

When the MRAM cell operates in a read mode, a sensing voltage is appliedto the bit line 72, the source region 52S is grounded, and a readvoltage is applied to the word line to turn on the access transistor TA.When the tunneling layer pattern 67 which depends on the magnetizationdirection of the free layer pattern 68 has a low magnetoresistancevalue, a relatively large current will flow through the bit line 72.When, on the other hand, the tunneling layer pattern 67 which depends onthe magnetization direction of the free layer pattern 68 has a highmagnetoresistance value, a relatively small current will flow throughthe bit line 72. Consequently, by means of the sensing voltage, themagnetization direction of the free layer pattern 68 may be identifiedfrom the value of the current which flows through the bit line 72.

Descriptions will be made on program and read operations of thesemiconductor memory device with reference to FIGS. 3 and 4.

When main cells MC1, MC2, MC3, MC4 and reference cells TC1, TC2, TC3,TC4 comprise MRAM cells. a first digit line D1 and a second digit lineD2 are disposed in a direction crossing the bit lines MB1, MB2, TB1,TB2. The MRAM cells are arranged at intersections of the bit lines MB1,MB2, TB1, TB2 and the digit lines D1 and D2, respectively. As describedabove, each MRAM cell includes an MTJ and an access transistor TA. Thetop electrode 69 of each MTJ is connected to one of the bit lines M1,MB2, TB1, TB2, and gate electrodes of the access transistors TA areconnected to one of the word lines W1, W2.

The first main cell MC1 and the first reference cell TC1 operate as onememory cell pair and the second main cell MC2 and the second referencecell TC2 operate as a second memory cell pair. For example, whencomplementary information is programmed in the pair comprising firstmain cell MC1 and first reference cell TC1, a digit line program currentis applied to the first digit line D1 and a bit line program current isapplied to the first main bit line MB1 while another bit line programcurrent flowing in a direction opposite to the bit line program currentis concurrently applied to the first reference bit line TB1 and thefirst sense amplifier S1 is turned off. Magnetic fields are induced tothe first main bit line MB1 and the first reference bit line TB1 indirections opposite to each other, so that the free layer patterns builtin the first main cell MC1 and the first reference cell TC1 aremagnetized in directions opposite to each other. No current is appliedto the second main bit line MB2 that is disposed between the first mainbit line MB1 and the first reference bit line TB1 in the exemplaryembodiment of FIG. 3, in order to reduce or prevent interference betweenthe first main bit line MB1 and the first reference bit line TB1.

In order to read the stored data, a read voltage is applied to the firstword line W1, and a sensing voltage is applied to the first main bitline MB1 and the first reference bit line TB1. The current flowingthrough the first main bit line MB1 and the current flowing through thefirst reference bit line TB1 are compared by the sense amplifier S1 suchthat the two currents are read as one bit of data.

FIG. 5 is a distribution chart of bit failures that occurred during aseries of program and read tests. In FIG. 5, curve 1 charts the bitfailures for a prior art semiconductor memory device in which the mainbit line and the reference bit line are disposed adjacent to each other,whereas, curve 2 charts the bit failures for a semiconductor memorydevice according to embodiments of the present invention in whichanother bit line is disposed between the main bit line and the referencebit line.

The semiconductor devices that were used in the tests of FIG. 5 usedMRAM cells that used a cobalt iron boron (CoFeB) layer as the free layerpattern. In these devices, the bit lines were fabricated to have a widthof 1 um and the distance between adjacent bit lines was 0.2 μm.

In FIG. 5, the horizontal axis of the chart indicates the bit failurerate (as a percentage), which means the rate of the failed bits resultedfrom the read results of data programmed within the semiconductor memorychips. The longitudinal axis indicates a chip cumulative frequency rate(as a percentage), which is the cumulative frequency rate of thesemiconductor memory chips used for the test.

As shown in FIG. 5, the bit failure rate of the semiconductor memorydevice fabricated in accordance with an embodiment of the presentinvention (curve 2) is relatively low. For example, with the prior artsemiconductor memory device, the bit failure rate at the point of 50% ofthe chip cumulative frequency rate is 80% (see curve 1). In other words,50% of the chips fabricated in accordance with the prior art areanalyzed to have failed bits of at least 50%. In contrast, the bitfailure rate at the point of 50% of the chip cumulative frequency rateis 32% (see curve 2) when a device in accordance with an embodiment ofthe present invention is used. That is, 50% of the chips fabricated inaccordance with an exemplary embodiment of the present invention werefound to have failed bits of 32% or less. Consequently, semiconductormemory devices fabricated in accordance with the embodiments of thepresent invention which have a structure where at least one bit line isdisposed between the main bit line and the reference bit line mayexhibit improved performance characteristics.

According to embodiments of the present invention, one or moreadditional bit lines may be disposed between a main bit line and areference bit line which operate as a bit line pair. During operation ofthe main bit line and the reference bit line, electrical signals are notapplied to the one or more other bit lines that are disposed between themain bit line and the reference bit line. Accordingly, interferencebetween the main bit line and the reference bit line may be reduced orprevented. Consequently, the distance between bit lines may bedecreased, thereby allowing increased rates of device integration.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe followings claims.

1. A semiconductor memory device, comprising: a cell array region, thecell array region including: a plurality of word lines that extend in afirst direction; a plurality of bit lines that extend in a seconddirection, the plurality of bit lines including a plurality of main bitlines and a plurality of reference bit lines; a plurality of main cellsthat are arranged adjacent to one another in the second direction, eachof the plurality of main cells being connected to a respective one ofthe word lines and a respective one of the main bit lines; and aplurality of reference cells that are arranged adjacent to one anotherin the second direction, each of the plurality of reference cells beingconnected to a respective one of the word lines and a respective one ofthe reference bit lines, wherein each of the main cells is paired with arespective one of the reference cells to provide a plurality of cellpairs, wherein two of the plurality of cell pairs are arranged adjacentto each other in the second direction.
 2. The semiconductor memorydevice of claim 1, wherein the main bit lines and the reference bitlines are parallel with each other.
 3. The semiconductor memory deviceof claim 1, wherein the main cells are disposed at main intersections ofthe word lines and the main bit lines.
 4. The semiconductor memorydevice of claim 3, wherein the reference cells are disposed at referenceintersections of the word lines and the reference bit lines.
 5. Thesemiconductor memory device of claim 1, wherein each of the plurality ofcell pairs is configured to store a single bit of data.
 6. Thesemiconductor memory device of claim 5, wherein two adjacent ones of theplurality of reference cells are disposed between two of the pluralityof main cells in the first direction.
 7. The semiconductor memory deviceof claim 1, further comprising a first sense amplifier region that isdisposed at one side of the cell array region in the second direction,the first sense amplifier region including a first sense amplifier thatis electrically connected to one of the main bit lines and to one of thereference bit lines.
 8. The semiconductor memory device of claim 7,wherein the first sense amplifier region further includes a second senseamplifier that is electrically connected to another one of the main bitlines and to another one of the reference bit lines.
 9. Thesemiconductor memory device of claim 8, wherein one of the main bitlines and one of the reference bit lines cross in the first senseamplifier region.
 10. The semiconductor memory device of claim 9,wherein the one of the main bit lines and the one of the reference bitlines cross in a second sense amplifier region and wherein the secondsense amplifier region is disposed opposite the first sense amplifierregion across the cell array region.
 11. The semiconductor memory deviceof claim 1, wherein the main cells and the reference cells areresistance memory cells.
 12. A semiconductor memory device, comprising:a cell array region, the cell array region including: a plurality ofword lines that extend in a first direction; a plurality of bit linesthat extend in a second direction, the plurality of bit lines includinga plurality of main bit lines and a plurality of reference bit lines; aplurality of main cells that are arranged adjacent to one another in thesecond direction, each of the plurality of main cells being connected toa respective one of the word lines and a respective one of the main bitlines; and a plurality of reference cells that are arranged adjacent toone another in the second direction, each of the plurality of referencecells being connected to a respective one of the word lines and arespective one of the reference bit lines, wherein each of the maincells is paired with a respective one of the reference cells to providea plurality of cell pairs, wherein a first and second of the pluralityof main cells are disposed immediately adjacent to each other in thefirst direction, a first and second of the plurality of reference cellsare disposed immediately adjacent to each other in the first direction,and the second of the plurality of main cells is disposed immediatelyadjacent to the first of the plurality of reference cells in the firstdirection.
 13. The semiconductor memory device of claim 12, wherein themain bit lines and the reference bit lines are parallel with each other.14. The semiconductor memory device of claim 13, wherein the main cellsand the reference cells are resistance memory cells, and wherein each ofthe plurality of cell pairs is configured to store a single bit of data.15. The semiconductor memory device of claim 14, further comprising afirst sense amplifier region that is disposed at one side of the cellarray region in the second direction, the first sense amplifier regionincluding a first sense amplifier that is electrically connected to oneof the main bit lines and to one of the reference bit lines.
 16. Thesemiconductor memory device of claim 15, wherein the first senseamplifier region further includes a second sense amplifier that iselectrically connected to another one of the main bit lines and toanother one of the reference bit lines.
 17. The semiconductor memorydevice of claim 16, wherein one of the main bit lines and one of thereference bit lines cross in the first sense amplifier region.
 18. Thesemiconductor memory device of claim 17, wherein the one of the main bitlines and the one of the reference bit lines cross in a second senseamplifier region and wherein the second sense amplifier region isdisposed opposite the first sense amplifier region across the cell arrayregion.
 19. A semiconductor memory device, comprising: a cell arrayregion, the cell array region including: word lines that extend in afirst direction; bit lines that extend in a second direction, the bitlines including a first main bit line, a second main bit line, a firstreference bit line and a second reference bit line; a first main celland a second main cell that are arranged immediately adjacent to eachother in the first direction, the first main cell being connected to oneof the word lines and the first main bit line, and the second main cellbeing connected to one of the word lines and the second main bit line;and a first reference cell and a second reference cell that are arrangedimmediately adjacent to each other in the first direction, the firstreference cell being connected to one of the word lines and the firstreference bit line, and the second reference cell being connected to oneof the word lines and the second reference bit line, wherein the firstmain cell is paired with the second main cell to provide a main cellpair and the first reference cell is paired with the second referencecell to provide a reference cell pair adjacent to the main cell pair inthe first direction.
 20. The semiconductor memory device of claim 19,wherein the second main cell and the first reference cell are arrangedimmediately adjacent to each other.